![]() ![]() ![]() Logic transistor density scaling comes from reducing these two dimensions. Angstronomics will use the following descriptor for node dimensions: This gives the unit cell area which can be used to determine density. The key dimensions to note in transistor area scaling is the Contacted Gate Pitch (CGP, historically poly pitch CPP) in the horizontal x-direction, and Cell Height in the vertical y-direction. Designers build standard logic circuits within these rows like Inverters, NAND gates, adders and flipflop cells that serve Boolean logic functions. Standard cells are organized into horizontal rows. Modern process technology uses Complementary Metal Oxide Semiconductor transistors, mixing PMOS and NMOS to create logic circuits. These assumed numbers have been with us for years, even ASML themselves showed just recently that foundry 5nm is over 180 MTr/mm² (relevant slide at the bottom of this article).ĬMOS FinFET standard cell diagram from imec (SPIE 2019) We will explain how transistor density is calculated below. With nothing else to work with, the density claim was simply multiplied with known TSMC 7nm densities to arrive at numbers like 171 Million Transistors per square mm (MTr/mm²). Since then, TSMC’s public disclosures left us with varying 1st party logic density improvement claims, from 1.7x to 1.84x, leading to many incorrect density assumptions from media and even industry. The paper seemed to have passed muster only because it was about the world’s most advanced process technology. Scotten Jones and David Schor expressed that the paper was more marketing than technical. Their IEDM 2019 paper about N5 was accepted which contained no transistor dimensions. Information for calculating transistor density has not gone far beyond the ‘1.8x vs N7‘ that TSMC said 4 years ago. TSMC has remained very tight lipped on technical details about N5. ![]()
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